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Freescale Semiconductor StarCore SC140 manuály

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Freescale semiconductor StarCore SC140 Uživatelský manuál (760 strany)


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Tabulka s obsahem

SC140 DSP Core

1

Table of Contents

3

StarCore Registry

11

List of Figures

13

List of Tables

15

List of Examples

19

About This Book

23

Abbreviations

24

NMI Non-maskable interrupt

25

Revision History

26

Chapter 1

27

Introduction

27

Architectural Differentiation

28

Core Architecture Features

29

Chapter 2

33

Core Architecture

33

StarCore

34

2.1.1.1 Data Register File

35

2.1.1.4 Shifter/Limiters

35

2.1.2.2 Bit Mask Unit (BMU)

36

2.1.6 Memory Interface

37

2.2 DALU

38

D0–D15, respectively

39

2.2.1.5 Scaling

46

2.2.1.6 Limiting

46

Table 2-9. Limiting Example

48

2.2.2.1 Data Representation

49

2.2.2.2 Data Formats

50

≤ SF ≤+1.0 - 2

50

≤ UI ≤ [2

51

2.2.2.3 Multiplication

52

2.2.2.4 Division

52

2.2.2.5 Unsigned Arithmetic

52

2.2.2.6 Rounding Modes

53

Multiply

58

40-bit Accumulate

58

Register Shifter

58

>> 16

58

2.3 Address Generation Unit

63

PABXABBXABA

64

Address Generation Unit

65

2.3.2 AGU Programming Model

66

MOVE.L #ADDRESS, B0

67

MOVE.W (R8), D0

67

2.3.2.2.2 Initializing ESP

68

2.3.3 Addressing Modes

70

2.3.3.3 PC Relative Mode

72

2.3.3.5 Memory Access Width

74

Yes √ (Rn) + Ni

76

(Rn+N0) Yes √ (Rn + N0)

76

2.3.4 Address Modifier Modes

77

2.3.6 Bit Mask Instructions

81

2.3.7 Move Instructions

83

MOVE.4F (R0),D0:D1:D2:D3

86

2.4 Memory Interface

87

2.4.1 SC140 Endian Support

88

2.4.1.2 Memory Organization

89

2.4.1.3 Data Moves

90

039 32 16

98

Chapter 3

101

Control Registers

101

Table 3-2. EMR Description

108

3.2 PLL and Clock Registers

110

Chapter 4

111

Emulation and Debug (EOnCE)

111

Interface

112

JTAG TAP Controller

113

EOnCE2 EOnCEn-1 EOnCEn

113

Table 4-3. JTAG Scan Paths

115

CHOOSE_CLOCK_DR signal

116

Bits 7-8 = 00

118

4.3.1 EOnCE Signals

120

4.3.3 Debug State

121

4.3.4 Debug Exception

122

4.3.6 Software Downloading

122

4.3.7 EOnCE Events

124

4.3.8 EOnCE Actions

125

4.5.1 EOnCE Controller

126

4.5.2 Event Counter

128

>=<

132

• Greater than

133

(EDCA).”

133

4.5.4 Event Selector (ES)

135

4.5.5 Trace Unit

136

-12 on page 4-31 to the

140

LSB part + 2

140

Software

141

4.6.2 Real-Time JTAG Access

143

EOnCE Register Addressing

144

Table 4-13. ECR Description

146

Table 4-14. ESR Description

148

EOnCE Controller Registers

153

4.7.6 EE Signals

154

4.8 Event Counter Registers

160

TEST EXT ECNTEN ECNTWHAT

161

4.8.4 EC Signals

163

Registers

164

EDCAi_REFB)

167

AWS EDCDEN CCS ATS

168

Event Selector (ES) Registers

171

BIT 7 6 5 4 3 2 1 BIT 0

172

SELDTB SELETB SEDLDI SELDM

172

TYPE rw rw rw rw rw rw rw rw

172

RESET 0 0 0 0 0 0 0 0

172

Register (ESEL_DI)

174

(ESEL_ETB)

174

4.11 Trace Unit Registers

175

+ +- - +

176

BITS 15-8 7 6 5 4 3 2 1 BIT 0

177

RESET 0 0 0 0 0 0 0 0 0

177

Trace Unit Registers

179

Chapter 5

181

Program Control

181

Pipeline

182

Table 5-1. Pipeline Example

183

5.1.1.3 Address Generation

184

5.2 Instruction Grouping

185

5.2.1 Grouping Types

186

5.2.1.1 Serial Grouping

187

5.2.1.2 Prefix Grouping

187

5.2.2 Prefix Types

188

5.2.3 Conditional Execution

189

Instruction Grouping

191

Position 0 1 2 3 4 5 6 7

193

MOVE #xxxx,D0 MOVE #xxxx,D1

193

5.3 Instruction Timing

194

— MOVE.L d0,(Rn + N0)

195

— MOVE.L d0,(Rn + $5)

195

— MOVE.L d0,(Rn + Rm)

195

— MOVE.L d0,(SP + $100)

195

Instruction Timing

196

MOVE.W (R0+N0),D0 ;delay slot

197

5.3.2.2 Delayed COF

199

5.3.3 Memory Access Timing

201

5.4 Hardware Loops

205

Hardware Loops

206

5.4.4 Loop Nesting

208

Example 5-12. Long Loop

210

5.5 Stack Support

212

Stack Support

216

5.6 Working Modes

217

5.6.3.1 Dual-stack RTOS

218

Exception Mode

219

Working Modes

220

5.7 Processing States

221

5.7.3 Execution State

223

5.7.4 Reset Processing State

223

5.7.5 Debug State

224

5.7.6 Wait Processing State

224

5.7.7 Stop Processing State

225

5.8 Exception Processing

226

Exception Processing

228

Priority

229

5.8.3 Maskable Interrupts

230

5.8.5 Internal Exceptions

230

5.8.5.1 Illegal Exception

231

5.8.5.2 DALU Overflow

232

5.8.5.3 TRAP Exception

232

5.8.5.4 Debug Exception

232

5.8.7 Exception Timing

233

Chapter 6

237

6.2.1 Single ISAP

238

6.2.2 Multiple ISAP

239

6.4 ISAP Memory Access

240

ISAP-core register transfers

241

6.7.3 Conditional Execution

246

6.8 Programming Rules

247

Programming Rules

248

Chapter 7

251

VLES Grouping Semantics

252

7.3 SC140 Pipeline Exposure

253

7.4.2 Sequencing Rules

254

7.4.3 Register Read/Write

254

7.4.4 Status Bit Updates

255

7.4.5 Instruction Words

255

7.4.6 MOVE-like Instructions

255

7.4.8.1 COF Instructions

256

7.4.9.1 Delay Slot

256

7.4.10 Hardware Loops

257

7.5.2 General Grouping Rules

258

Rule G.G.4

259

Rule G.G.4 Exceptions

260

7.5.3 Prefix Grouping Rules

261

Rule G.P.1

262

Rule G.P.3

263

Rule G.P.4

263

Rule G.P.5

263

Rule G.P.6

264

Rule G.P.7

264

Rule G.P.8

265

Rule G.P.9

265

7.5.4 AGU Rules

266

Rule A.2

267

Rule A.3

267

Rule A.4

268

7.5.5 Delayed COF Rules

269

Rule D.2

270

Rule D.3

270

Rule D.4

271

Rule D.5

271

Rule D.5a

271

Rule D.6

271

7.5.6 Status Bit Rules

272

Rule T.2.a

273

Rule T.2.b

273

Rule T.2.c

273

Rule SR.2

273

Static Programming Rules

274

Rule SR.3

276

Rule SR.4

276

Rule SR.4a

277

7.5.7 Loop Nesting Rules

278

Rule L.N.2

279

Rule L.N.3

279

7.5.8 Loop LA Rules

281

Rule L.L.3

282

Rule L.L.4

282

7.5.9 Loop Sequencing Rules

283

Rule L.D.3

284

Rule L.D.5

284

Rule L.D.6

284

Rule L.D.7

285

Rule L.D.8

285

Rule L.D.9

285

7.5.10 Loop COF Rules

286

Rule L.C.5

287

Rule L.C.7

288

Rule L.C.9

289

Rule L.C.10

289

7.5.11 General Looping Rules

290

7.6.1 AGU Dynamic Rules

291

7.6.2 Memory Access Rules

292

7.6.3 RAS Rules

293

7.6.4 Loop Rules

293

Dynamic Programming Rules

294

Rule SR.2a

296

Rule SR.4b

296

Rule SR.6

296

Rule A.1a

297

7.7 Programming Guidelines

298

Rule J.5

299

Rule L.N.5

299

Programming Guidelines

300

7.8 LPMARK Rules

301

7.8.3.1 LPMARK Notation

302

7.8.3.2 Loop Nesting Rules

303

7.8.3.3 Loop LA Rules

303

LPMARK Rule L.L.2

304

LPMARK Rule L.L.3

304

LPMARK Rule L.L.5

304

LPMARK Rule L.L.6

305

LPMARK Rule L.D.2 + L.D.3

305

LPMARK Rule L.D.6

305

LPMARK Rule L.D.8 + L.D.9

305

7.8.3.5 Loop COF Rules

306

LPMARK Rule L.C.3 + L.C.5

307

LPMARK Rule L.C.9

308

LPMARK Rule L.C.10

308

LPMARK Rule L.C.11 + L.C.12

309

LPMARK Rule L.G.3 + L.G.4

309

LPMARK Rule SR.6

309

7.9 NOP Definition

310

7.9.1 Grouping Examples

311

NOP Definition

312

[IFT CLR D0IFT NOP IFT NOP]

313

Appendix A

315

A.1.1 Conventions

316

M0-M3 Modulo registers

317

{0 ≤u3 < 2

318

, L}. The values for

318

Table A-4. Assembler Syntax

318

A.1.4 Encoding Notation

320

A.1.5 Prefix Word Encoding

321

Instruction Fields

322

A.1.5.2 Two-Word Prefix

323

DSP Core Instruction Set

324

A.1.6 Instruction Types

326

A.2 Instructions

333

ABS Absolute Value (DALU) ABS

334

ADD Add (DALU) ADD

338

Example 2

339

ADDA Add (AGU) ADDA

343

Example 1

344

#s16 + Da → Dn

350

ADDNC.W #s16,Da,Dn

350

ADR Add and Round (DALU) ADR

352

AND Bitwise AND (DALU) AND

354

Example 3

355

Description

359

Operation Assembler Syntax

359

ASL Arithmetic Shift Left ASL

362

Rx<<2 → Rx

364

ASL2A Rx

364

Rx<<1 → Rx

365

01516313239 C

371

15 8 7 0

373

BF Branch If False (AGU) BF

379

BFD <label

381

BFD >label

381

SR[1] T True bit

381

$00E0 0000

381

Bit-Masked Change a BMCHG

383

16-Bit Operand (BMU)

383

Bit-Masked Test a BMTSTC.W

405

$24A6 --0010 0100 1010 0110

406

Bit-Masked Test a BMTSTS

408

16-Bit Operand If Set (BMU)

408

Bit-Masked Test a BMTSTS.W

410

BRA Branch (AGU) BRA

413

Source Code Comments

415

BT Branch If True (AGU) BT

423

BTD <label

425

BTD >label

425

$00E0 0002

425

CLB Da,Dn

427

$00000 F7434

427

$0:$FF FFFF FFF5

427

SR[0] C Clears the carry bit

429

$00E0 0001 $00E0 0000

429

CMPEQ Da,Dn

431

000 D0 010 D2 100 D4 110 D6

432

001 D1 011 D3 101 D5 111 D7

432

CMPEQA rx,Rx

435

Dn > Da → T

437

CMPGT Da,Dn

437

Rx > rx → T

441

CMPGTA rx,Rx

441

CONTD label

449

DEBUG 1 2 4 1001111001110000

451

where #u5 = 1

453

DECEQ Dn

455

DECEQA Rx

457

Dn – 1 → Dn; Dn≥0 → T

458

DECGE Dn

458

DI 1 1 4 1001111101111101

463

Divide Iteration (DALU) DIV

464

DOSETUPn label

475

$0000 0002

475

$0000 1020

475

EI Enable Interrupts (AGU) EI

477

EOR Da,Dn

479

$FF FFFF FFFB

479

IADDNC.W #s16,Dn

489

Request (AGU)

492

Da,Da jj Data Register Pairs

496

Da.L * Db.L → Dn

501

IMPY Da,Db,Dn

501

#s16 * Dn.L → Dn

503

IMPY.W #s16,Dn

503

IMPYSU Da,Db,Dn

507

$00 0000 0122

507

$FF FFFF FFFF

507

$0:$FF FFFF FEDE

507

IMPYUU Da,Db,Dn

509

Dn + 1 → Dn

511

Dn + $00:00010000 → Dn

513

INC.F Dn

513

Rx + 1 → Rx

515

INSERT Da,Db,Dn

517

JF Jump If False (AGU) JF

519

JMP Jump (AGU) JMP

523

JMPD label {0 ≤ label < 2

525

JSRD label {0 ≤ label < 2

529

JT Jump If True (AGU) JT

531

Prefix Formats and Opcodes

537

$AAAA AAAA $5555 5555

541

542

0.000 0000 0000 1000 0000

551

1.111 1111 1111 1111 1000

554

$FFFF 8000

554

MARK 1 1 4 1001111001110010

559

Dg,Dh GG Data Register Pairs

560

MAX Dg,Dh

560

$FF FFFF FFF5

560

MAX2 Transfer Two 16-Bit MAX2

561

MAX2VIT MAX2 MAX2VIT

563

MAXM Dg,Dh

565

$FF FFFF FFDD

565

MIN Dg,Dh

567

$00 36AE 3FB4

567

respective data register

572

MOVE.B Byte Move (AGU) MOVE.B

578

MOVE.B (SP+s15),DR

579

MOVE.B DR,(SP+s15)

579

Move Fractional Word MOVE.F

582

MOVE.F Db,(ea)

583

Move Long Word (AGU) MOVE.L

586

0write1read

588

MOVE.L (SP+s15),Do.E

590

MOVE.L Move Long (AGU) MOVE.L

593

MOVE.L (SP+s15),C4

595

MOVE.L C4,(SP+s15)

595

$0000 0050

600

MOVES.4F

618

MOVES.L Move Long to MOVES.L

619

Memory (AGU)

621

#u32 → Db

625

MOVEU.L #u32,Db

625

Memory to a Register (AGU)

629

Rn RRR Address Register

632

Da.H * Db.H → Dn

633

MPY Da,Db,Dn

633

NEG Negate (DALU) NEG

645

NOP No Operation (PREFIX) NOP

647

~Da → Dn

648

NOT Da,Dn

648

NOT DR.L

650

NOT DR.H

650

Da ⏐ Dn → Dn

654

OR Da,Dn

654

RND Round (DALU) RND

673

01516313239

676

[3] NMID Cleared

690

SAT.L Dn

694

$0000 0004

694

STOP 1 8 4 1001111101111001

702

SUB Subtract (DALU) SUB

703

SUBA Subtract (AGU) SUBA

708

(2 * Dn) – Da → Dn

710

SUBL Da,Dn

710

TFR Da,Dn

718

TFRA rx,Rx

720

TFRA OSP,Rn

722

TFRA Rn,OSP

722

TSTEQ Dn

728

TSTGE Dn

731

TESTGEA.L Rx

732

TSTGT Dn

734

TSTGTA Rx

735

WAIT 1 8 4 1001111101111000

741

Appendix B

747

Table B-1. SCID Assignments

748

Index I-1

749

I-2 Index

750

Index I-3

751

I-4 Index

752

, A-275, A-279

753

I-6 Index

754

Index I-7

755

I-8 Index

756

Index I-9

757

I-10 Index

758




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