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Exception Processing

SC140 DSP Core Reference Manual 5-53

5.8.6.2 Exception Mode Execution

An exception mode execution is performed in exactly the same way as a normal program flow. There is no

constraint on the length of an exception routine. Table 5-20 shows the flow for the pipeline changing from

normal execution to exception execution.

5.8.7 Exception Timing

When an unmasked exception is taken, the core breaks the normal execution flow and adds a cycle. The

return PC and SR are pushed onto the stack, and the core then resumes execution at the exception vector

address. After the exception request is asserted, the exact point at which the normal execution flow is

interrupted is not fixed. It is dependent on the properties of the instructions being executed in the vicinity

of the exception request as well as any core stalls that may occur in parallel. For example, a delayed

instruction and its delay slot constitute an uninterruptable sequence.

Example 5-17 describes the exception servicing for a simple case that does not include delayed

instructions or core stalls, but does include exceptions occurring near change-of-flow instructions. In this

example, the JUMP instruction represents all change-of-flow instructions in Table 5-8, excluding delayed

instructions and TRAP. It also represents the DI (disable interrupt) instruction.

Example 5-17. Basic Exception Timing

Let ES0 -> ... -> ES4 ... be a sequence of execution sets such that if ES0 is a JUMP instruction, then ES1 is

an instruction from the target address (ES0 -> ES1 -> ES2 -> ES3 -> ES4). In addition, assume that an

exception request arises on the same cycle that ES0 starts its AGU execution stage.

If (ES1 is not JUMP) and (ES2 is not JUMP):

Then

• The execution set from the target of the exception vector is executed after ES2, and the address of

ES3 is pushed as a return address to the stack.

• 1 cycle is added, which is needed to push the return address to the stack.

Else, if (ES1 is not JUMP) and (ES2 is JUMP):

Table 5-20. Exception Pipeline

Operation

Instruction Cycle

123456789101112

Pre-fetch n1 n2 n3 i1 i2

Fetch n1 n2 n3 i1 i2

Decode n1 n2 push i1 i2

Address

Generation

n1 n2 push i1 i2

Execute n1 n2 push i1 i2

n = normal or user execution set

i1, i2 = exception execution sets 1 and 2

1 2 ... 228 229 230 231 232 233 234 235 236 237 238 ... 759 760

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