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DMA Timers (DTIM0–DTIM3)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
22-4 Freescale Semiconductor
22.2.2 DMA Timer Extended Mode Registers (DTXMRn)
The DTXMRn register programs DMA request and increment modes for the timers.
Table 22-2. DTMRn Field Descriptions
Field Description
15–8
PS
Prescaler value. The prescaler is programmed to divide the clock input (internal bus clock/(16 or 1) or clock on
DTINn) by values from 1 (PS equals 0x00) to 256 (PS equals 0xFF).
7–6
CE
Capture edge.
00 Disable capture event output
01 Capture on rising edge only
10 Capture on falling edge only
11 Capture on any edge
5
OM
Output mode.
0 Active-low pulse for one internal bus clock cycle (-ns resolution at MHz).
1 Toggle output.
4
ORRI
Output reference request, interrupt enable. If ORRI is set when DTERn[REF] is set, a DMA request or an interrupt
occurs, depending on the value of DTXMRn[DMAEN] (DMA request if set, interrupt if cleared).
0 Disable DMA request or interrupt for reference reached (does not affect DMA request or interrupt on capture
function).
1 Enable DMA request or interrupt upon reaching the reference value.
3
FRR
Free run/restart
0 Free run. Timer count continues incrementing after reaching the reference value.
1 Restart. Timer count is reset immediately after reaching the reference value.
2–1
CLK
Input clock source for the timer
00 Stop count
01 Internal bus clock divided by 1
10 Internal bus clock divided by 16. This clock source is not synchronized with the timer; therefore, successive
time-outs may vary slightly.
11 DTINn pin (falling edge)
0
RST
Reset timer. Performs a software timer reset similar to an external reset, although other register values can be written
while RST is cleared. A transition of RST from 1 to 0 resets register values. The timer counter is not clocked unless
the timer is enabled.
0 Reset timer (software reset)
1 Enable timer
IPSBAR
Offset:
0x00_0402 (DTXMR0)
0x00_0442 (DTXMR1)
0x00_0482 (DTXMR2)
0x00_04C2 (DTXMR3)
Access: User read/write
76543210
R
DMAEN HALTED
00000
MODE16
W
Reset:00000000
Figure 22-3. DTXMRn Registers
- MCF52211 ColdFire 1
- Integrated 1
- How to Reach Us: 2
- Chapter 2 3
- Signal Descriptions 3
- Freescale Semiconductor ii 4
- Chapter 6 5
- Freescale Semiconductor iv 6
- Freescale Semiconductor v 7
- Freescale Semiconductor vii 9
- Freescale Semiconductor viii 10
- Chapter 22 11
- DMA Timers (DTIM0–DTIM3) 11
- Chapter 23 12
- Chapter 24 12
- UART Modules 12
- Chapter 25 13
- C Interface 13
- Chapter 26 14
- Chapter 27 15
- Chapter 28 15
- Debug Module 15
- Chapter 29 16
- Chapter 1 17
- Overview 17
- 1.2 Block Diagram 19
- 1.2 Features 20
- Freescale Semiconductor 1-5 21
- 1-6 Freescale Semiconductor 22
- Freescale Semiconductor 1-7 23
- 1.2.1 V2 Core Overview 24
- 1.2.2 Integrated Debug Module 24
- 1.2.3 JTAG 25
- 1.2.4 On-Chip Memories 26
- 1.2.5 Power Management 26
- Freescale Semiconductor 1-11 27
- 1.2.14 Real-Time Clock (RTC) 28
- 1.2.17 Backup Watchdog Timer 29
- 1.2.20 DMA Controller 29
- 1.2.21 Reset 29
- 1.2.22 GPIO 30
- 2.3 Pin Functions 32
- Freescale Semiconductor 2-7 37
- 2.4 Reset Signals 38
- 2.6 Mode Selection 38
- Table 2-5. Clocking Modes 39
- C I/O Signals 40
- 2.11 DMA Timer Signals 40
- 2.12 ADC Signals 41
- 2.15 Debug Support Signals 41
- 2.17 Power and Ground Pins 43
- 2-14 Freescale Semiconductor 44
- Chapter 3 45
- ColdFire Core 45
- 3-2 Freescale Semiconductor 46
- 3.2.1 Data Registers (D0–D7) 48
- 3.2.5 Program Counter (PC) 50
- 3.2.7 Status Register (SR) 51
- 3.3 Functional Description 52
- 3.3.4 Processor Exceptions 61
- 3.3.4.5 Privilege Violation 63
- 3.3.4.9 Debug Interrupt 64
- 3.3.4.13 Interrupt Exception 65
- 3.3.4.14 Fault-on-Fault Halt 65
- 3.3.4.15 Reset Exception 65
- 3.3.5.1 Timing Assumptions 69
- 3-32 Freescale Semiconductor 76
- Chapter 4 77
- 4.2.2 Mask Register (MASK) 80
- 4.3 Functional Description 82
- 4.3.1.1 Rounding 83
- 4.3.1.3 MULS/MULU 84
- 4.3.4 Data Representation 85
- 4.3.5 MAC Opcodes 85
- Chapter 5 91
- Static RAM (SRAM) 91
- 5.3.2 Power Management 94
- 6.4 Low-Power Mode Operation 96
- 6.5 Block Diagram 97
- 6.6 Signal Descriptions 99
- 6.7 Memory Map and Registers 100
- 0x12_0000 (SYNCR) 101
- Clock Module 102
- 0x12_0002 (SYNSR) 103
- 0x12_0004 (ROCR) 105
- 0x12_0007 (LPDR) 105
- 0x12_0008 (CCHR) 106
- 0x12_0009 (CCLR) 107
- 0x12_000A (OCHR) 108
- 0x12_000B (OCLR) 108
- 0x12_0012 (RTCCR) 109
- 0x12_0013 (BWCR) 110
- 6.8 Functional Description 111
- 6.8.3 System Clock Generation 112
- 6.8.4 PLL Operation 112
- 6.8.4.5 PLL Lock Detection 114
- Freescale Semiconductor 6-21 115
- ≠ Feedback Count 115
- 6.8.4.9 Loss of Clock Reset 116
- 6-28 Freescale Semiconductor 122
- Chapter 7 123
- 7.2.1 Memory Map 124
- 0x14_0000 (WCR) 125
- 0x14_0002 (WMR) 126
- 0x14_0004 (WCNTR) 127
- 0x14_0006 (WSR) 127
- 7.3 Functional Description 128
- Chapter 8 129
- Power Management 129
- 0x000C (PPMRH) 130
- 0x0018 (PPMRL) 132
- 0x0012 (LPICR) 134
- 0x0021 (PPMRS) 135
- 0x0022 (PPMRC) 136
- 0x11_0007 (LPCR) 136
- 8.3 IPS Bus Timeout Monitor 137
- 8.4 Functional Description 138
- 0x0023 (IPSBMT) 138
- 8.4.1.1 Run Mode 139
- 8.4.1.2 Wait Mode 139
- 8.4.1.3 Doze Mode 139
- 8.4.1.4 Stop Mode 139
- 8.4.1.5 Peripheral Shut Down 139
- 8.4.2.1 ColdFire Core 140
- 8.4.2.6 I 141
- C Module 141
- 8.4.2.10 I/O Ports 142
- 8.4.2.11 Reset Controller 142
- 8.4.2.13 Clock Module 142
- 8.4.2.14 Edge Port 142
- 8.4.2.16 PWM Module 143
- 8.4.2.17 BDM 143
- 8.4.2.18 JTAG 143
- Chapter 9 145
- 9.2.1 RCON 146
- 9.2.2 CLKMOD[1:0] 146
- 9.2.3 JTAG_EN 146
- 9.2.4 TEST 146
- 9.3.1 Programming Model 146
- 9.3.2 Memory Map 147
- 9.3.3 Register Descriptions 147
- 9-6 Freescale Semiconductor 150
- Chapter 10 151
- Reset Controller Module 151
- 10.4 Signals 152
- 10.5 Memory Map and Registers 152
- 10.6 Functional Description 155
- 10-6 Freescale Semiconductor 156
- 10.6.2 Reset Control Flow 157
- 10-8 Freescale Semiconductor 158
- 10.6.3 Concurrent Resets 159
- 10.6.3.2 Reset Status Flags 160
- Chapter 11 161
- Real-Time Clock 161
- Use Access 162
- 0x03C0 (HOURMIN) 163
- 0x03C4 (SECONDS) 164
- 0x03C8 (ALRM_HM) 165
- 0x03CC (ALRM_SEC) 166
- 0x03D0 (RTCCTL) 167
- 0x03D4 (RTCISR) 168
- 0x03DC (STPWCH) 170
- 0x03E0 (DAYS) 171
- 0x03E4 (ALRM_DAY) 172
- 0x03F4 (RTCGOCU) 172
- 11.3 Functional Description 173
- 0x03F8 (RTCGOCL) 173
- 11.3.2 Alarm 174
- 11.3.3 Minute Stopwatch 174
- 11-16 Freescale Semiconductor 176
- Chapter 12 177
- System Control Module (SCM) 177
- Table 12-1. SCM Register Map 178
- 12.5 Register Descriptions 179
- [31:24] [23:16] [15:8] [7:0] 179
- 0x0000 (IPSBAR) 180
- 0x0008 (RAMBAR) 181
- 0x0010 (CRSR) 182
- 0x0011 (CWCR) 183
- 12.6 Internal Bus Arbitration 185
- 12.6.2 Arbitration Algorithms 186
- 0x001C (MPARK) 187
- 12.7.1 Overview 188
- 12.7.2 Features 188
- 0x0020 (MPR) 190
- 0x0030 (GPACR0) 192
- Modules Protected 194
- Chapter 13 195
- General Purpose I/O Module 195
- 13.2 Overview 196
- 13.3 Features 196
- 13.4 Signal Descriptions 196
- 31–24 23–16 15–8 7–0 197
- 13.6 Register Descriptions 198
- 0x10_0014 (PORTDD) 198
- 0x10_000E (PORTTA) 198
- 0x10_000C (PORTQS) 199
- 0x10_0008 (PORTNQ) 199
- 0x10_000B (PORTAS) 199
- 0x10_002C (DDRDD) 200
- 0x10_0026 (DDRTA) 200
- 0x10_0024 (DDRQS) 200
- 0x10_0020 (DDRNQ) 200
- 0x10_0023 (DDRAS) 201
- 0x10_0044 (PORTDDP/SETDD) 201
- 0x10_003E (PORTTAP/SETTA) 202
- 0x10_003C (PORTQSP/SETQS) 202
- 0x10_0038 (PORTNQP/SETNQ) 202
- 0x10_003B (PORTASP/SETAS) 202
- 0x10_005C (CLRDD) 203
- 0x10_0056 (CLRTA) 203
- 0x10_0054 (CLRQS) 204
- 0x10_0050 (CLRNQ) 204
- 0x10_0053 (CLRAS) 204
- 0x10_0074 (PDDPAR) 205
- 0x10_0070 (PTDPAR) 205
- 0x10_006C (PQSPAR) 206
- 0x10_006B (PASPAR) 206
- 0x10_006E (PTAPAR) 206
- 0x10_0068 (PNQPAR) 207
- 0x10_0078 (PSRR) 208
- 13.7 Ports Interrupts 209
- 0x10_007C (PDSR) 209
- 13-16 Freescale Semiconductor 210
- Chapter 14 211
- Interrupt Controller Module 211
- 14.2 Memory Map 214
- 14.3 Register Descriptions 215
- 0x0C00 (IPRHn) 216
- 0x0C04 (IPRLn) 216
- 0x0C08 (IMRHn) 217
- 0x0C0C (IMRLn) 218
- 0x0C10 (INTFRCHn) 219
- 0x0C14 (INTFRCLn) 219
- 0x0C18 (IRLRn) 220
- 0x0C19 (IACKLPRn) 220
- 14.3.6.1 Interrupt Sources 223
- Freescale Semiconductor 14-17 227
- 14-18 Freescale Semiconductor 228
- Chapter 15 229
- 15-2 Freescale Semiconductor 230
- 15.1.2 USB On-The-Go 231
- 15.2 Functional Description 232
- 15.3.5 USB Transaction 236
- 15.4.1 Capability Registers 238
- 7 654 3 210 239
- OTG_INT_STAT register 241
- 7 6543210 242
- 76543210 243
- Figure 15-19. Status Register 249
- 76 5 43210 250
- Figure 15-21. ADDR Register 251
- Page Register 1 252
- Register 253
- Figure 15-25. TOKEN Register 254
- 0x1C_00B4 (BDT_PAGE_03) 256
- 0x1C_00C0 (ENDPT0) 257
- 0x1C_0108 (USB_OTG_CONTROL) 261
- 15-34 Freescale Semiconductor 262
- Freescale Semiconductor 15-35 263
- 15.7 On-The-Go Operation 264
- B cable 266
- 15.7.3 Power 267
- 15.7.4 USB Suspend State 268
- Chapter 16 269
- Edge Port Module (EPORT) 269
- 16.2 Low-Power Mode Operation 270
- Chapter 17 275
- DMA Controller Module 275
- 17.1.2 Features 276
- 17.2 DMA Transfer Overview 277
- [31:24] [23:16] [15:8] [7:0] 278
- 0x00_0014 (DMAREQC) 278
- 0x00_0100 (SAR0) 279
- 0x00_0104 (DAR0) 280
- 0x00_0108 (BCR0/DSR0) 280
- See Figure 17-6 (DSRn) 281
- 0x00_010C (DCR0) 282
- 17.4 Functional Description 285
- 17-12 Freescale Semiconductor 286
- Freescale Semiconductor 17-13 287
- 17.4.4 Data Transfer 288
- 17.4.5 Termination 289
- 17-16 Freescale Semiconductor 290
- Chapter 18 291
- ColdFire Flash Module (CFM) 291
- 18.1.2 Features 292
- COMMON FLASH BUS 292
- INTERNAL FLASH BUS 292
- 18.3.1 Memory Map 293
- (from PROGRAM_ARRAY_BASE) 294
- Register Bits 296
- 0x1D_0000 (CFMMCR) 297
- 0x1D_0002 (CFMCLKD) 298
- 0x1D_0008 (CFMSEC) 299
- 0x1D_0010 (CFMPROT) 300
- PROTECT[31:0] — 301
- 0x1D_0014 (CFMSACC) 302
- 0x1D_0018 (CFMDACC) 303
- 0x1D_0020 (CFMUSTAT) 303
- 0x1D_0024 (CFMCMD) 305
- 18.4 Functional Description 306
- 0x1D_004A(CFMCLKSEL) 306
- 18.4.2 Flash Normal Mode 307
- 18-20 Freescale Semiconductor 310
- Freescale Semiconductor 18-21 311
- 18-22 Freescale Semiconductor 312
- Freescale Semiconductor 18-23 313
- Page Erase 314
- Freescale Semiconductor 18-25 315
- Mass Erase 316
- Freescale Semiconductor 18-27 317
- 18-28 Freescale Semiconductor 318
- 18.4.2.4 Stop Mode 319
- 0x0407, security is 320
- 18.4.3.2 Blank Check 321
- 18-32 Freescale Semiconductor 322
- Chapter 19 323
- 19.3.1 Overview 324
- 19.4 Command Definition 325
- Access: read/write 326
- 19.4.1.5 Read Data 328
- 19.4.1.7 Page Program 328
- 19.5 Functional Description 329
- Chapter 20 331
- 0x15_0000 (PCSR0) 333
- 0x15_0002 (PMR0) 334
- 20.3 Functional Description 335
- 0x15_0004 (PCNTR0) 335
- 20.3.3 Timeout Specifications 336
- 20.3.4 Interrupt Operation 336
- Freescale Semiconductor 20-7 337
- 20-8 Freescale Semiconductor 338
- Chapter 21 339
- 21.3 Block Diagram 340
- 21.4 Low-Power Mode Operation 341
- 21.5 Signal Description 341
- 21.6 Memory Map and Registers 342
- 0x1A_0000 (GPTIOS) 343
- 0x1A_0001 (GPCFORC) 344
- 0x1A_0002 (GPTOC3M) 344
- 0x1A_0003 (GPTOC3D) 345
- 0x1A_0004 (GPTCNT) 345
- 0x1A_0006 (GPTSCR1) 346
- 0x1A_0008 (GPTTOV) 347
- 0x1A_0009 (GPTCTL1) 347
- 0x1A_000B (GPTCTL2) 348
- 0x1A_000C (GPTIE) 348
- 0x1A_000D (GPTSCR2) 349
- 0x1A_000E (GPTFLG1) 350
- 0x1A_000F (GPTFLG2) 350
- 0x1A_0010 (GPTC0) 351
- 0x1A_0018 (GPTPACTL) 351
- 0x1A_0019 (GPTPAFLG) 352
- GPTPAFLG 353
- 21.7 Functional Description 354
- 0x1A_001D (GPTPORT) 354
- 0x1A_001E (GPTDDR) 354
- 21.7.1 Prescaler 355
- 21.7.2 Input Capture 355
- 21.7.3 Output Compare 355
- 21.7.4 Pulse Accumulator 356
- 21.7.5 Event Counter Mode 356
- 21.8 Reset 359
- 21.9 Interrupts 359
- 21.9.4 Timer Overflow (TOF) 360
- 22.1.2 Features 362
- 0x00_0400 (DTMR0) 363
- 0x00_0402 (DTXMR0) 364
- 0x00_0403 (DTER0) 365
- 0x00_0404 (DTRR0) 367
- 0x00_0408 (DTCR0) 367
- 22.3 Functional Description 368
- 0x00_040C (DTCN0) 368
- 22.4.1 Code Example 369
- 23.1.2 Overview 372
- 23.1.3 Features 372
- 23.1.4 Modes of Operation 372
- Table 23-2. QSPI Memory Map 373
- 1514131211109876543210 375
- 15 141312 11 109876543 210 376
- 23.4 Functional Description 379
- 23-10 Freescale Semiconductor 380
- 23.4.1 QSPI RAM 381
- 23.4.2 Baud Rate Selection 382
- 23.4.3 Transfer Delays 383
- 23.4.4 Transfer Length 384
- 23.4.5 Data Transfer 384
- Freescale Semiconductor 23-15 385
- 23-16 Freescale Semiconductor 386
- 24.1.2 Features 388
- 0x00_0200 (UMR10) 391
- 0x00_0200 (UMR20) 392
- 0x00_0204 (USR0) 394
- 0x00_0204 (UCSR0) 395
- 0x00_0208 (UCR0) 396
- 0x00_020C (URB0) 398
- 0x00_020C (UTB0) 398
- 0x00_0210 (UIPCR0) 398
- 0x00_0210 (UACR0) 399
- 0x00_0214 (UISR0) 400
- 0x00_0218 (UBG10) 401
- 0x00_021C (UBG20) 401
- 0x00_0234 (UIP0) 401
- 24.4 Functional Description 402
- 0x00_0238 (UOP10) 402
- 24.4.1.1 Programmable Divider 403
- 24.4.2.1 Transmitter 404
- Freescale Semiconductor 24-19 405
- 24.4.2.2 Receiver 406
- 24.4.2.3 FIFO 407
- 24.4.3 Looping Modes 408
- 24.4.3.1 Automatic Echo Mode 409
- 24.4.3.2 Local Loopback Mode 409
- 24.4.3.3 Remote Loopback Mode 409
- 24.4.4 Multidrop Mode 410
- UMR1n[PM] = 11 411
- 24.4.5 Bus Operation 412
- Table 24-13. UART Interrupts 413
- Freescale Semiconductor 24-29 415
- 24-30 Freescale Semiconductor 416
- Freescale Semiconductor 24-31 417
- 24-32 Freescale Semiconductor 418
- Freescale Semiconductor 24-33 419
- 24-34 Freescale Semiconductor 420
- 25.1.1 Block Diagram 422
- 25.1.2 Overview 422
- 25.1.3 Features 423
- 0x0300 (I2ADR0) 424
- 0x0304 (I2FDR0) 425
- 0x0308 (I2CR0) 426
- 0x030C (I2SR0) 427
- 25.3 Functional Description 428
- 0x0310 (I2DR0) 428
- 25.3.3 Data Transfer 429
- 25.3.4 Acknowledge 430
- 25.3.5 STOP Signal 430
- 25.3.6 Repeated START 430
- Figure 25-10. Repeated START 431
- 25-12 Freescale Semiconductor 432
- 25.4.2 Generation of START 433
- 25.4.4 Generation of STOP 434
- 25.4.6 Slave Mode 435
- 25.4.7 Arbitration Lost 435
- C Interrupt Routine 436
- 26.3 Block Diagram 438
- 16 R/W 0x0000 26.4.11/26-17 439
- 0x19_0000 (CTRL1) 439
- 0x19_0002 (CTRL2) 442
- 0x19_0004 (ADZCC) 444
- 0x19_0006 (ADLST1) 445
- 0x19_0008 (ADLST2) 445
- 0x19_000A (ADSDIS) 447
- 0x19_000C (ADSTAT) 447
- 0x19_000E (ADLSTAT) 449
- 0x19_0010 (ADZCSTAT) 450
- 0x19_0012 (ADRSLT0) 451
- 0x19_0022 (ADLLMT0) 452
- 0x19_0032 (ADHLMT0) 452
- 0x19_0052 (POWER) 454
- 0x19_0054 (CAL) 456
- 26.5 Functional Description 457
- 26.5.1 Input MUX Function 459
- 26.5.2 ADC Sample Conversion 461
- 26.5.2.1 Single-Ended Samples 462
- 26.5.2.2 Differential Samples 462
- 26.5.3 ADC Data Processing 463
- 26.5.5 Scan Sequencing 465
- 26-30 Freescale Semiconductor 466
- Table 26-21. ADC Scan Modes 467
- 26.5.7 Interrupt Sources 468
- 26.5.8 Power Management 468
- Freescale Semiconductor 26-33 469
- 26.5.9 ADC Clock 470
- 26.5.11 Supply Pins V 474
- Table 27-1. PWM Memory Map 476
- 0x1B_000C (PWMCNT0) 484
- 0x1B_0014 (PWMPER0) 485
- 0x1B_001C (PWMDTY0) 485
- 27.3 Functional Description 487
- 27-14 Freescale Semiconductor 488
- 27.3.2 PWM Channel Timers 489
- PWMCAE = 1 490
- PWMCAE = 0 490
- 27.3.2.4 PWM Timer Counters 491
- 27.3.2.5 Left-Aligned Outputs 492
- Freescale Semiconductor 27-19 493
- 27.3.2.7 PWM 16-Bit Functions 494
- 27.3.2.8 PWM Boundary Cases 495
- 28.2 Signal Descriptions 498
- 28.3 Real-Time Trace Support 499
- 28.4.1 Shared Debug Resources 503
- WDMREG command 507
- 28.5.1 CPU Halt 515
- 28.5.2 BDM Serial Interface 516
- 28.5.3 BDM Command Set 518
- Freescale Semiconductor 28-25 521
- RAREG/RDREG) 522
- WAREG/WDREG) 523
- Command Formats: 525
- READ is not executed 526
- FILL Command Format 528
- Freescale Semiconductor 28-33 529
- 0x0 0xC 0x0 0x0 529
- 28-34 Freescale Semiconductor 530
- 0x00x00x00x0 530
- NEXT CMD 531
- CMD COMPLETE 531
- 28.6 Real-Time Debug Support 535
- DDATA[3:0] 536
- 28.6.1.1 Emulator Mode 537
- 28.7.1 User Instruction Set 538
- 29.1.2 Features 546
- 29.1.3 Modes of Operation 546
- 29.2.1 JTAG Enable (JTAG_EN) 546
- 29.3.2 IDCODE Register 548
- 29.3.3 Bypass Register 549
- 29.3.5 TEST_CTRL Register 549
- 29.3.6 Boundary Scan Register 549
- 29.4 Functional Description 550
- 29.4.3 JTAG Instructions 551
- 29.4.3.1 IDCODE Instruction 552
- 29.4.3.3 EXTEST Instruction 552
- 29.4.3.6 HIGHZ Instruction 553
- 29.4.3.8 CLAMP Instruction 553
- 29.5.1 Restrictions 554
- Appendix A 555
- Registers 0-7 ADOFS0-7 16 570
- Appendix B 575
- Revision History 575
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